The present invention relates to a nonvolatile memory device such as an EPROM (erasable and electrically programmable ROM).
In a typical EPROM, memory cells made up of double gate construction MISFET's (metal insulated semiconductor field effect transistors) having a floating gate and a control gate are arrayed in the vertical and lateral directions. Control signals based on address signals to the X decoders are selectively applied to the control gates of the memory cells in the X direction through a common word line, and control signals based on address signals to the Y decoders are selectively applied to the drains of the memory cells in the Y direction through a common bit line, to thereby perform the writing and reading operations. In the thus constructed EPROM, a large amount of electric power is consumed if peripheral circuits such as decoders are constituted by MISFET's having channels of the same conductivity type. The inventors of the present invention therefore have attempted to reduce the power consumption by constructing the peripheral circuits using CMOS (complementary metal oxide semiconductor) FET's.
Through their study, however, the inventors of the present invention have found that if the peripheral circuits are made up of CMOSFET's, an N-channel MISFET of the depletion mode which is used as a resistance element in a pull-up circuit which is connected between the word line and the power supply terminal V.sub.PP for charging the word line, permits a large amount of current to flow from the word line into the X decoder particularly when the data is to be read, and makes it difficult to achieve the object of reducing the power consumption. More specifically, a transfer gate (MISFET of the depletion mode) connected between the X decoder and the word line on a non-selected line is rendered conductive when the data is to be read. Therefore, a potential difference equal to the reading voltage (V.sub.PP =5 volts) appears across the resistor. However, since the MISFET in the pull-up circuit has a small resistance, the electric current easily flows from the power supply terminal V.sub.PP to the X decoder via the MISFET, word line and transfer gate. The current flowing through each word line amounts to about 10 .mu.A. Therefore, in a typical EPROM of this structure the total current can easily amount to about 5 mA. The same phenomenon also appears when the MISFET of the depletion mode is used as a resistance element in the pull-up circuit on the side of the Y decoders. Namely, extra current flows into the Y decoder when the data is to be read, resulting in the increase in the consumption of electric current (electric power).
To reduce the consumption of current when the data is to be read, and to reduce the consumption of electric power by the EPROM, it can be attempted to reduce the ratio (W/L) of channel width of the MISFET to the channel length, such that the drain current is reduced. In this case, however, the only method is to increase the channel length since the channel width cannot be so reduced. Increase of the channel length, however, results in the increase of the area of MISFET and makes it difficult to integrate the device highly densely.
The inventors of the present invention therefore have studied the use of a P-channel MISFET of the enhancement mode as a resistance element instead of the N-channel MISFET of the depletion mode. In this case, the current could be prevented from flowing into the non-selected lines when the data was being read. However, use of a writing voltage V.sub.PP of as great as 25 volts or 21 volts during the writing operation invited the occurrence of latch-up phenomenon causing the elements to be damaged. That is, parasitic transistors of the PNP- and NPN-type are formed by the diffusion regions, semiconductor substrates and wells of the N-channel MISFET and P-channel MISFET, and a PNPN thyristor structure is rendered conductive (occurrence of latch-up phenomenon) by the parasitic transistors being triggered by a high voltage applied to the parasitic transistors.